The invention relates to a device for the synchronization of a clock signal used in a semiconductor chip with a predetermined clock signal with the simultaneous adjustment of the duty cycle of the clock signal. The invention in particular relates to a device for the synchronization of the clock signal used internally in a semiconductor chip with a clock signal supplied to the semiconductor chip from outside, wherein the length of the duty cycle of the clock signal is adjusted simultaneously.
In semiconductor devices, in particular in memory devices such as DRAMs (DRAM=Dynamic Random Access Memory and/or dynamic read write memory) that are, for instance, based on CMOS technology, clock signals are used for the chronological co-ordination of the processing and/or relaying of the data. Conventional semiconductor devices in general use a “single ended” clock signal CLK that is present on a single line for this purpose.
The data are then, for instance, relayed or processed at the respective rising edge of the single-ended clock signal CLK (or, alternatively, e.g., at the respective falling edge of the single-ended clock signal).
Furthermore, DDR devices, in particular DDR-DRAMs (DDR-DRAM=Double Data Rate DRAM) are known from prior art. In prior art DDR devices, the data are processed at both clock edges, so that the data are relayed and/or processed both at the rising and at the falling edges of the clock signal.
This means that data are relayed and/or processed more frequently and/or faster (in particular twice as frequently and/or twice as fast) in a DDR device than with corresponding, conventional devices in which the processing and/or relaying is performed at one of the clock signal edges only.
The clock signal supplied to such devices has a very high frequency. Therefore, to increase the insensitivity to disturbances, the clock signal may once be supplied to the device as clock signal CLK and, in parallel, as inverted clock signal bCLK on a further line, so that two clock signal lines are guided to the device.
In the case of systems that are clocked this way it is, on the one hand, important that signals that are output by the semiconductor device are always output at the same clock frequency as the input clock signal CLK, i.e. are present at the outputs of the semiconductor chip with the same clock frequency as the input clock signal CLK. On the other hand, the signals also have to be coordinated in time with the input clock signal CLK such that the edges of the output signals coincide in time with the edges of the input clock CLK, so that the signals are synchronized for the further processing in a subsequent device. The output signals of such a device thus may not include any phase shifting vis-à-vis the supplied input clock signal.
On the other hand, it is necessary for DDR devices that, if possible, an equal amount of time passes between the edges of the clock signals CLK or bCLK, respectively, so that both clock states—high and low—have the same duration. The “duty cycle” that is defined as the relation of the duration of the positive signal portion, i.e. high, to the clock length of the clock signal, should consequently be 50%.
The clock signal used in a DDR semiconductor chip thus has to be synchronized with the externally present clock signal CLK and furthermore has to include a duty cycle of exactly 50%. This applies in analogy for the inverted clock signal bCLK.
The external clock signal(s), i.e. the clock signal CLK and the inverted clock signal bCLK, is/are generated by an appropriate external clock signal generator connected with the device.
For the desired synchronization of the clock signal DQS or of the inverted clock signal bDQS used in the semiconductor device with the externally supplied input clock signals CLK or bCLK, the use of a clock signal synchronizer, for instance, a delay locked loop (DLL) is known from prior art. Such a DLL delays the externally supplied clock signal CLK or bCLK such that this delay effects, along with the inherent clock delay that will inevitably occur in the subsequent semiconductor device, that the edges of the output signals of the semiconductor device are synchronized with the edges of the clock signal CLK or bCLK and do not exhibit any phase shifting, i.e. coincide in time. In the case of frequency changes of the clock signals CLK or bCLK, the clock signals DQS or bDQS used in the semiconductor device are correspondingly readjusted in the delay. Such as DLL circuit is, for instance, known from EP 964 517.
A clock signal synchronizer includes, for instance, a first delay means (delay chain) which the external clock signal CLK or bCLK is fed to as input signal and which delays same. The output clock signal of the delay means is supplied—usually both to an off-chip driver (OCD) and, at any rate, also—to a feedback delay element. In the feedback delay element, there are reproduced the delay characteristics of the semiconductor device that follows the device in the signal path of the output clock signal and for which the input clock signal CLK is to be synchronized. The feedback delay element is thus a second delay means and delays the signal supplied thereto—ideally—like the semiconductor device that obtains the output signal of the device as clock signal. The output signal (FB) of the feedback delay element is fed to a phase comparing means, e.g., a comparator or phase detector, as input signal, which compares the signal FB with the input clock signal CLK. The output signal of the phase comparing means which describes the phase shifting between the signals FB and CLK is fed to a control element that adjusts, via an appropriate control signal, the delay effected in the first delay element (delay chain) to the desired value. If the phase of the FB signal is faster than the CLK signal, the control element effects a step-wise increase of the delay via an increment signal. In analogy, if the phase of the FB signal is slower than the CLK signal, the control element effects, by means of a decrement signal signalized to the first delay element, the decreasing of the delay. This control cycle of the delay locked loop (DLL) thus effects that the signal output by the OCD is delayed vis-à-vis the input clock signal as described above and as desired.
Such a clock signal synchronizer—the functioning of which has been described in a strongly abbreviated manner—does, however, have the disadvantage that the duty cycle of the output clock signal is not changed, but has the value of the input clock signal CLK fed to the device.
For adapting the duty cycle, there are, for instance known circuits from prior art which are connected in series to a clock signal synchronizer, i.e. a DLL, in the path of a clock signal. Such an adaptation of the duty cycle which is separate from the adaptation of the delay does, however, illustrate disadvantages vis-à-vis a combination in a circuit. In the case of an integration of a duty cycle corrector (DCC) in a DLL, at least the input and output stages that are required for level adaptation could, for instance, be used jointly.
For these and other reasons, there is a need for the present invention.